Two dimensional magnetic recording system, devices and methods

ABSTRACT

This application includes systems and techniques relating to storage devices, such as a device including: a first read channel to process a first input signal obtained from a storage medium using a first read head; a second read channel to process a second input signal obtained from the storage medium using a second read head, which is offset from the first read head in each of two dimensions; a single digital timing loop configured to control interpolation of timing of sampling for first and second analog to digital converters in the first and second read channels; and a two dimensional equalizer coupled with output lines of the first and second read channels; the device being configured to account for a fractional timing difference between the first input signal and the second input signal, the fractional timing difference being a fractional amount of a single clock cycle of the device.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application (and claims the benefitof priority under 35 USC 120) of U.S. application Ser. No. 14/749,492,filed Jun. 24, 2015, issuing as U.S. Pat. No. 9,431,052 on Aug. 30,2016, which claims the benefit of the priority of U.S. ProvisionalApplication Ser. No. 62/017,424, filed Jun. 26, 2014 and entitled “TWODIMENSIONAL MAGNETIC RECORDING SYSTEM”, which is incorporated herein byreference.

BACKGROUND

The present disclosure describes systems and techniques relating tostorage devices, such as Two Dimensional Magnetic Recording (TDMR)storage devices.

Various mediums are used to create storage devices for use in computingsystems. In magnetic-medium-based storage devices, data can be stored oncircular, concentric tracks on a magnetic disk surface. A read-writehead can retrieve and record data on a magnetic layer of a rotating diskas the head flies on a cushion of air over the disk surface. Whenretrieving data, magnetic field variations can be converted into ananalog electrical signal, which can then be amplified and converted to adigital signal for signal processing.

To increase the amount data that is stored in magnetic recordingsystems, smaller amounts of the magnetic medium have been employed tostore each respective bit of data by using a smaller read-write head andcorresponding track pitch, and by reducing the size of guard bands oneither side of each track. As the recording densities have increased,various error correction techniques have been employed to assist inreading back the bits of data. In addition, in order to increaserecording densities still further, some have proposed Shingled MagneticRecording (SMR) to shrink the track pitch still further and remove theguard bands between tracks, which allows more tracks to fit on therecording medium. In SMR, the tracks are written so that one trackpartially overlaps the previous track.

Further, some have also proposed Two Dimensional Magnetic Recording(TDMR) to use in conjunction with SMR. As the track pitch gets smallerin SMR, at some point the one dimensional (1D) codes and detectors willnot be able to handle the Inter Track Interference (ITI) from tracksadjacent to the one being read. In a 1D channel, the ITI negativelyimpacts performance. But in a two dimensional (2D) channel, the ITI canpotentially assist in making the bit decisions when reading data from amagnetic medium.

SUMMARY

The present disclosure describes systems and techniques relating tostorage devices, such as storage devices that employ Two DimensionalMagnetic Recording (TDMR) media, devices and systems. According to anaspect of the described systems and techniques, a device includes: afirst read channel to process a first input signal obtained from a TwoDimensional Magnetic Recording (TDMR) storage medium using a first readhead, wherein the first read channel includes a first analog to digitalconverter (ADC); a second read channel to process a second input signalobtained from the TDMR storage medium using a second read head, whereinthe second read channel includes a second ADC; and a single digitaltiming loop (DU) for both the first read channel and the second readchannel, wherein the single DTI, is configured to control interpolationof timing of sampling for the first and second ADCs.

The device can also include a two dimensional equalizer coupled withoutput lines of the first read channel and the second read channel,wherein the first read head and the second read head are offset fromeach other in each of two dimensions. The first read channel can furtherinclude a first asymmetry correction block (ASC), a first variable gainamplifier (VGA), a first programmable delay line, and first finiteimpulse response filter (FIR); the second read channel can furtherinclude a second ASC, a second VGA, a second programmable delay line,and a second FIR; and FIR taps for the first FIR can be copied from thefirst FIR to the second FIR so the first FIR and the second FIR act asduplicates of each other.

The first read channel can further include a first asymmetry correct onblock (ASC), a first variable gain amplifier (VGA), and a firstprogrammable delay line; the second read channel can further include asecond ASC, a second VGA, and a second programmable delay line; and thedevice can further include a finite impulse response filter connectedwith an output line of the first programmable delay line the finiteimpulse response filter lying outside of the first read channel andbeing configured and arranged to generate an error signal to drive theASCs and VGAs of the first and second read channels, and to drive thesingle DTL.

The first read channel can further include a first asymmetry correct onblock (ASC), a first variable gain amplifier (VGA), and a firstprogrammable delay line; the second read channel can further include asecond ASC, a second VGA, and a second programmable delay line; and thedevice can be configured and arranged to generate an error signal froman output of the two dimensional equalizer to drive the ASCs and VGAs ofthe first and second read channels, and to drive the single DM.

The device can include a single interpolator controlled by the singleDTL to perform the same interpolation of timing of sampling for thefirst and second ADCs for both the first read channel and the secondread channel; and coefficients on taps of respective FIR filters in thetwo dimensional equalizer can be adjusted to account for a timingdifference between the first input signal and the second input signal,wherein the timing difference is a fractional amount of a single clockcycle of the device, the fractional amount being less than the time ofthe single clock cycle.

The above aspects described with respect to a device, can also beimplemented as systems and methods. The first read channel, the secondread channel, the single DTL, and the two dimensional equalizer caninclude circuitry located in a hard disk controller for a TDMR storageapparatus, the hard disk controller being included on a system on chip.A system can include: a Two Dimensional Magnetic Recording (TDMR)storage apparatus including a magnetic media disk, which is mounted on aspindle and motor assembly, and a head assembly including at least afirst read head and a second read head, wherein the first read head andthe second read head are offset from each other in each of twodimensions; and a storage controller coupled with the TDMR storageapparatus, the storage controller including a first read channel toprocess a first input signal obtained from the magnetic media disk ofthe TDMR storage apparatus using the first read head, and a second readchannel to process a second input signal obtained from the magneticmedia disk of the TDMR storage apparatus using the second read head;wherein the first read channel includes a first analog to digitalconverter (ADC), the second read channel includes a second ADC; andwherein the storage controller includes a single digital timing loop(DTL) for both the first read channel and the second read channel, thesingle DTL being configured to control interpolation of timing ofsampling for the first and second ADCs, and the storage controllerincludes a two dimensional equalizer coupled with output lines of thefirst read channel and the second read channel. Moreover, the storagecontroller can include features of the device, and in someimplementations, the storage controller is integrated with the TDMRstorage apparatus.

According to another aspect of the described systems and techniques, amethod includes: processing, in a Two Dimensional Magnetic Recording(TDMR) device, a first analog read signal and a second analog readsignal from a first portion and a second portion, respectively, of aTDMR storage medium, wherein each of the first portion and the secondportion at least partially overlap with a track on the TDMR storagemedium, and the processing includes separate analog to digitalconversions of the respective first and second analog read signals;performing a single interpolation of timing of sampling for each of theseparate analog to digital conversions; filtering digital output signalsof the separate analog to digital conversions in a TDMR equalizer; andadjusting coefficients of filters in the TDMR equalizer to account for atiming difference between the first and second analog read signals.

The timing difference can be a fractional amount of a single clock cycleof the TDMR device, the fractional amount being less than the time ofthe single clock cycle. Alternatively, the timing difference can be morethan a fractional amount of a single clock cycle of the TDMR device. Forexample, if the Hits are sufficiently long, integer amounts (plusfractional amounts) of up to 1 or 2 cycles of delay difference can behandled by the FIR structure. With longer FIRs, even more than 2 clockcycles can theoretically be handled.

The method can include generating an error signal from an output of theTDMR equalizer to drive asymmetry correction and variable gainamplification for both the first analog read signal and the secondanalog read signal, and to drive the single interpolation. The methodcan include: aligning a center of a first read head with a center of thetrack on the TDMR storage medium, the first analog read signal beingfrom the first read head; filtering a digital output signal of a firstof the separate analog to digital conversions using a finite impulseresponse filter; and generating an error signal from the filtereddigital output signal to drive asymmetry correction and variable gainamplification for both the first analog read signal and the secondanalog read signal, and to drive the single interpolation.

The method can include aligning a center of a first read head with acenter of the track on the TDMR storage medium, the first analog readsignal being from the first read head; wherein the processing canfurther include: delaying a first digital output signal of a first ofthe separate analog to digital conversions by a first programmed amountof time; delaying a second digital output signal of a second of theseparate analog to digital conversions by a second programmed amount oftime; filleting the first delayed digital output signal using a firstfinite impulse response filter; filtering the second delayed digitaloutput signal using a second finite impulse response filter; and copyingtaps from the first finite impulse response filter to the second finiteimpulse response filter so the first finite impulse response filter andthe second finite impulse response filter act as duplicates of eachother.

The described systems and techniques can be implemented in electroniccircuitry, computer hardware, firmware, software, or in combinations ofthem, such as the structural means disclosed in this specification andstructural equivalents thereof. This can include at least onecomputer-readable medium embodying a program operable to cause one ormore data processing apparatus (e.g., a signal processing deviceincluding a programmable hardware processor) to perform operations insupport of the systems and devices, or simulations thereof for use indesign of such systems and devices. Moreover, method implementations canbe realized from a disclosed system, apparatus or device, and system,apparatus or device implementations can be realized from a disclosedmethod.

The disclosed embodiments below can be implemented in various systemsand apparatus, including, but not limited to, a special purpose dataprocessing apparatus (e.g., a wireless access point, a remoteenvironment monitor, a router, a switch, a computer system component, amedium access unit), a mobile data processing apparatus (e.g., awireless client, a cellular telephone, a personal digital assistant(PDA), a mobile computer, a digital camera a general purpose dataprocessing apparatus (e.g., a minicomputer, a server, a mainframe, asupercomputer), or combinations of these.

The described systems and techniques can result in one or more of thefollowing advantages. The design of front end loops for TDMR readchannels, and control thereof, can be made easier. Loop latency can belowered. Hardware costs can be reduced. In addition, synchronization ofdata paths in TDMR read channels can be simplified. For example, readsignals need not be fully aligned before being processed by a twodimensional equalizer, which can handle some of the signal alignmentbefore the two signals are combined to form a final output signal for atrack being read. Timing, gain, asymmetry, etc. frontend loops can runon the error signal generated using 2D equalizer output and itscorresponding Viterbi decisions, which is less noisy than an errorsignal generated using 1D FIR samples.

Details of one or more implementations are set forth in the accompanyingdrawings and the description below. Other features and advantages may beapparent from the description and drawings, and from the claims.

DRAWING DESCRIPTIONS

FIG. 1A shows an example of a data storage system.

FIGS. 1B-1C show examples of writing data using Shingled MagneticRecording (SMR) systems and techniques.

FIGS. 1D-1F show examples of reading data using Two Dimensional MagneticRecording (TDMR) systems and techniques.

FIG. 2A shows a first example of a system architecture for TDMR readcircuitry.

FIG. 2B shows a second example of a system architecture for TDMR readcircuitry.

FIG. 3A shows a third example of a system architecture for TDMR readcircuitry.

FIG. 3B shows a fourth example of a system architecture for TDMR readcircuitry.

FIG. 4 is a flowchart showing an example of reading stored data in aTDMR storage system.

Like reference numbers and designations in the various drawings indicatelike elements.

DETAILED DESCRIPTION

FIG. 1A shows an example of a data storage system 100. A host 110 iscoupled with a storage controller 120. The storage controller 120interfaces with a storage device 130 and is configured to employ one ormore of the systems and techniques described in this disclosure. Thestorage controller 120 can be implemented in various ways. For example,the storage controller 120 can include a printed circuit board (PCB)with various set of processing circuitries designed to handle designatedtasks. The storage controller 120 can also include registers, volatilememory, non-volatile memory, or a combination of these, which can beused to buffer user data, hold control data or code, or both. In someimplementations, the storage controller 120 includes a hardwareprocessor that is programmed to perform specified tasks by firmware,software, or a combination of these.

The storage controller 120 can include a hardware interface throughwhich commands from the host 110 can be received, and the storagecontroller 120 can decode such host commands and operate the storagedevice 130 in response thereto. The storage device 130 includes amagnetic recording medium, and can also include various additional typesof storage mediums, such as an optical medium, a solid state memorymedium (e.g., NAND-based flash memory), or a combination thereof. Insome implementations, the storage device 130 can be a hard disk drive(HDD). The storage device 130 can employ Shingled Magnetic Recording(SMR) and Two Dimensional Magnetic Recording (TDMR), which can beperformed using various structures, such as a HDD or a tape drive.Moreover, the storage controller 120 can include various modules, suchas a processing module, a control module, a detection module, and acompensation module, and the storage controller 120 can be a hard diskcontroller (HDC) and control HDD functions, such as controlling thespeed of a spindle motor, controlling a voice coil motor (VCM), andmanaging power consumption.

In some implementations, the storage device 130 includes a disk drivewith multiple magnetic media disks 132 mounted on an integrated spindleand motor assembly 134. The disk drive further includes ahead assembly136, which can include read signal circuitry, servo signal processingcircuitry, and write signal circuitry. The disk drive can also include aPCB, with various drive electronics (e.g., a printed circuit boardassembly (PCBA) with semiconductor devices). The magnetic media disks132 can be coated with a particulate surface or a thin-film surface andcan be written to, or read from, a single side or both sides of eachdisk. The head assembly 136 can include a preamp/writer, where headselection and sense current value(s) can be set, and the disk drive canbe a TDMR disk drive that operates as described in further detail below.

Although shown as separate elements in FIG. 1A, e.g., with signalsbetween the elements carried through a flexible printed cable, thevarious parts of the data storage system 100 can be integrated intovarious circuit devices, systems on chip, apparatus, or combinationsthereof. The storage control 120 can be integrated into the host 110 orinto the storage device 130. In general, the systems and techniquesdescribed herein can be implemented as one or more devices, such as oneor more integrated circuit (IC) devices, which may or may not becombined with a storage device at the point of sale.

The storage controller 120 can include a subset of the elements ascribedto it in various examples herein and/or other elements ascribed to thehost 110 or the storage device 130. Thus, in some implementations, thestorage controller 120 can be one or more IC chips (e.g., a combo chipor system on chip (SOC)), which can include read/write channel signalprocessing circuitry, which can further include error correctioncircuitry. The storage controller 120 can be a microprocessor and a harddisk controller, with associated read only memory (ROM) and randomaccess memory (RAM) or interfaces thereat.

FIG. 1B shows an example 140 of SMR, as can be used in the disk drive ofFIG. 1A. VCM 142 can be used to position an arm 144, and thus itsread-write head(s) 146, over a desired track. In variousimplementations, the read-write head(s) 146 can include various numbersof head elements with combined or dedicated functions. For example theread-mite head(s) 146 can include one or more readers and one writer. Asanother example, the read-write head(s) 146 can include a dedicatedwrite head and two or more separate, additional dedicated read heads.Moreover, although a single arm 144 is shown in FIG. 1B, in someimplementations more than one arm 144 (or other structures) can be used.

In a case, at least one of the read-write head(s) 146 can be used tomite a first track 150, followed by a second track 152, and a thirdtrack 154. Since SMR is used to write the tracks 150, 152, 154, wherethe sectors of each track (e.g., a sector 156 of track 154) are writtento partially overlap the previously written track, the track pitch 148is smaller than the write head. Thus, the process of writing sectors inSMR involves writing tracks in an overlapped fashion, which can bethought of as similar to installing shingles on the roof of a house. Insome cases, the sectors of one track are aligned with the sectors of aprevious, overwritten track, and in other cases, the sectors are notaligned between adjacent tracks, depending on the implementation.

Note that the amount of overlap between tracks can be substantial. FIG.1C shows a more detailed example 160 of writing data using SMR. A fluxinput to a write head 164 causes data to be encoded in the magneticorientation of the grains of a magnetic medium 166. Each final sector ofa shingled track 168 can be of a size matching only a far corner of thewrite head 164, as the head motion of the write head 164 lays down thetracks in progressive scans. Thus, a final shingled track 168 can besubstantially smaller in size than the write head 164 used to write thetrack 168.

Moreover, since the track pitch is so small, reading back the track 168can prove difficult, especially if the track pitch is smaller than theread head as well. Thus, in addition to 1D coding and decodingtechniques, where information coming from a downtrack direction for thetrack being read is used to decide a bit of read data, 2D coding anddecoding techniques can be used, where information coming from across-track direction for the track being read can also be used. Inessence, SMR can be used to decouple track width from writer sizethrough shingling (i.e., the track pitch does need not depend on thewidth of the write head), and TDMR can be used to decouple track widthfrom reader size using multiple reads (i.e., two or more read heads canread from two or more tracks at a time).

FIG. 11) shows an example of reading data using a TDMR system. MultipleSMR tracks 170 (Track k−2, Track k−1, Track k, and Track k+1) areencoded on a magnetic medium. A first read head 172 (H1) and a secondread head 174 (H2) are used to read a given track (e.g., Track k). Notethat the read heads 172, 174 are larger than the track pitch.Traditionally, the size of the read head would be than the track widthto prevent Inter Track Inference (ITI), but here the TDMR systemexploits ITI and effectively removes it. Thus, the read head need not besmaller than the track width.

As shown, H1 172 covers both Track k−1 and Track k and so obtains readsignal arising from both. Likewise, H2 174 also covers Track k−1 andTrack k and so obtains read signal arising from both, but in differentamounts than that of H1 172. Because of the overlap of the read heads172, 174 in the cross-track direction, the read heads 172, 174 must havean offset 176 between them in a downtrack direction. The amount of thisoffset 176 can vary with implementation. Moreover, while only two readheads 172, 174 are discussed here and below, it will be appreciated thatthe systems and techniques described herein are also applicable toimplementations using more than two read heads. In addition, thealignment of the read heads with respect to the tracks 170 (in thecross-track direction) can also be changed.

FIGS. 1E and 1F show examples of different alignment for read heads 182,186 for reading data using TDMR systems and techniques. In theseexamples, each of H1 182 and H2 186 are shown as having the same widthas the track being read, but in other implementations, these read heads182, 186 can also be larger than the track, as shown in FIG. 1D.Moreover, in some implementations, each of the read heads 182, 186 neednot have the same width as the other.

In a first configuration 180, H1 182 is largely on-track (e.g., the readhead 182 has its center 184 aligned with the center of the track), andH2 186 has a substantial portion that is off-track (e.g., the read head186 has its center 188 off the center of the track by an amount that isat least a quarter of the width of the read head 186). In a secondconfiguration 190, each of the read heads 182, 184 have the centers 184,188 not aligned with the center of the track being read.

Note that some implementations can use both configurations. This is moreof a choice of what give the best performance, and is a function of headseparation, track pitch, and bit length. In general, the two sensors(read heads) are separated along the track by some amount as indicatedby item 176 in FIG. 1D. Since the sensors are located towards the tip ofan actuator arm that swings to read tracks at an inner diameter (ID) ofa disk and all the way out to an outer diameter (OD). With differentangles of the actuator arm, the cross track separation changes.Therefore, an optimal alignment at ID, may be different from optimalalignment of medium diameter (MD) or OD, and a controller can bedesigned to change the reading technique being used in light of aparticular TDMR reading situation. 100431 in the first configuration180, shown in FIG. 1E, H1 182 is the primary read head, and H2 186 isthe secondary read head. In some implementations using this firstconfiguration 180, due to the large ITI noise that can be experienced bythe second reader 186, no decision driving timing/gain/baseline recoveryshould be performed on the corresponding read back signal from H2 186.Thus, rather than drive front end loops using H2 186, H1 182 isdesignated as the primary reader and all the front end loops (e.g.,timing loop, gain loop, and baseline loop) can be driven from the signalproduced by the primary reader 182. The read channel architecture can bedesigned to take advantage of this configuration 180.

In the second configuration 190, shown in FIG. 1F, neither of the readheads 182, 186 is assumed to be on-track, and both H1 182 and H2 186 canbe off-track. In this configuration 190, neither of the read heads 182,186 should be used as a primary reader, and gain and timing loopsshouldn't be driven from an error signal generated from either read headindividually since both signal will have large error. Rather, signalsfrom the two heads 182, 186 can be combined, and with ITI removed, thecombined and cleaned signal can be used to drive the front end loops.The read channel architecture can be designed to take advantage of thisconfiguration 190. For example, gain and timing recovery can be done ona common error signal generated at the output of a 2D equalizer, asdescribed in further detail below.

In addition, in either configuration 180, 190, the offset between theread heads 182, 186 in the cross-track direction can also be changed. Insome cases, the overlap between the read heads 182, 186 can besubstantial, i.e., more than half the width of one of the read heads,creating a narrow cross-track separation distance 192, e.g., an overlapthat is three quarters of a common read head width, as shown in FIG. 1E.In some case, the overlap between the read heads 182, 186 can be less,creating a wide cross-track separation distance 194, e.g., an overlapthat is less than half of a common read head width, as shown in FIG. 1F.Note that the cross-track separation can vary from ID to OD, and so thecontroller can be designed to optimize its read processing to accountfor changes from ID to OD.

FIG. 2A shows a first example 200 of a system architecture for TDMR readcircuitry. The TDMR architecture 200 includes first read channel 210that receives a first analog signal from a first read head, e.g., H1182. The TDMR architecture 200 also includes second read channel 230that receives a second analog signal from a second read head, e.g., H2186. Note that the TDMR architecture 200 can be designed to be used witheither read head configuration 180 (with a primary read head H1) or readhead configuration 190 (with no primary read head).

The first read channel 210 can include a High Pass Filter (HPF) 212, anAsymmetry Correction Block (ASC) 214, a Variable Gain Amplifier (VGA)216, and a Continuous Time Filter (CTF) 218. The first read channel 210can al s include an Analog to Digital Converter (ADC) 220, a delay line222, and a Finite Impulse Response (FIR) filter 226. The delay line 222can be a programmable delay line (DAN) with a register that can beloaded with a value N to delay the digital signal by a specified numberof clock cycles. As noted above, each of the read heads will beseparated by some distance, and so each will have their own data readpath, and their signals will need to be matched in time.

The second read channel 230 can have corresponding elements, includingHPF2 232, ASC2 234, VGA2 236, CTF2 238, ADC2 240, D^N2 242, and FIR2246. Note that which of the read heads H1 182 and H2 186 is leading andwhich is trailing will depend on their particular placement in the headassembly and the direction of disk rotation. In any case, theprogrammable delay lines 222, 242 can be programmed with appropriatevalues N (on input line 224) and N2 (on input line 244) to account fortiming differences between the two read signals that are integer amountsof the clock cycle, which is used by the TDMR device in which the readchannels 210, 230 reside, to match the two signals given theirleading/trailing offset.

The respective FIRs 226, 246 are used in TDMR architecture 200 toequalize the respective digital signals (the ADC samples) to respectivetargets, and their output lines are connected to 2D equalizer 250. The2D equalizer 250 operates to cancel the ITI and combine the digitalsignals in proper proportion. The 2D equalizer 250 can be two FIRfilters with their outputs added together. After this 2D equalizationand combination into a single output signal, the rest of the TDMRarchitecture 200 can include traditional elements of a ID architecture.

In some implementations, a Baseline Loop (BL) unit 260 can receive thecombined output signal of the D equalizer 250 and route the digitalsignal to a Linear Viterbi Detector (LVIT) 262 and to an adder throughwhich feedback is received from a Viterbi target filter (H) 264 that hasits input connected to an output of the LVIT 262, as shown in FIG. 2A.The output line of the LVIT 262 is also connected to additionalprocessing circuitry, such as a decoder 298, which can be an iterativeSOVA-LDPC (Soft Output Viterbi Algorithm—Low Density Parity-Check Code)decoder.

In some implementations of TDMR architecture 200, H1 182 is a primaryread head, and all the front end loops for control of separate readchannels 210, 230 are driven from H1 182. Thus, an output line of theFIR 226 can be routed to a BL unit 266 as show Output of the BL unit 266can be combined in an adder with output of H 264 (e.g., the linearViterbi decisions after passing through the Viterbi target filter) andused to create a single error signal to control an Adaptive FIR (AFIR)unit 268, a Digital Timing Loop (DTL) block 280, an Automatic GainControl (AGC) block 270, and an Asymmetry Management (ASM) block 274.

Note that a single DTL 280 can be used to control separate interpolators(ITERP 282 and ITERP2 284) that interpolate timing of sampling for ADCsin the respective first and second read channels 210, 230. In addition,only one AFIR unit 268 need be used (on the primary reader's branch)since it controls the FIR 226, and the same FIR taps can be copied 228from the FIR 226 to the FIR 246. Thus, the two FIRs 226, 246 act asduplicates of each other with the same filter coefficients, with eachFIR 226, 246 equalizing ADC samples (delayed as appropriate to look likethe target (used in data detection) convolved with data written on themedium (i.e., each FIR equalizes its signal to remove read noise and dothe channel shaping for the data detector). Due to this copying of thefilter taps, only one adaptive unit is needed to adapt the operation ofthe first FIR 226 since the second FIR 246 is effectively adapted by thecopying of the taps 228.

In other implementations of TDMR architecture 200, such as when usingthe no-primary head configuration 190 of FIG. 1F, not all of the frontend loops need be driven from an error signal generated from only onebranch. Since the second read channel 230 has its own FIR filter 246,one or more of the front end loops on either branch can be driven by itsown individual signal. Note that the TDMR, architecture 200 can bedesigned to switch between different operations modes for drivingdifferent parts of the front end loops, from one error signal from onechannel versus two errors signals from respective channels, depending onthe cross-track alignment of the read heads. For example, a second AGCcan control VGA2 236 and a second ASM can control ASC2, with both beingdrive by an error signal generated from an output of FIR2 246.

FIG. 2B shows a second example 290 of a system architecture for TDMRread circuitry. As noted above for the TDMR architecture 200, the TDMRarchitecture 290 can include a 2D equalizer 250 with two FIR filters,FIR1 252 and FIR2 254. However, rather than performing 2D equalizationon FIR samples equalized by front end FIR filters 226, 246 (i.e., usingfour FIR filters total) the TDMR architecture 290 performs 2Dequalization directly on ADC samples. This can result in lower looplatency and smaller hardware costs since only three FIR filters areused, rather than four.

Many of the components of the TDMR architecture 290 are the same as theTDMR architecture 200, as shown by common reference numbers, and so arenot described again here. As before, the 2D equalizer 250 can do FIRaveraging and combination of the two digital signals. Not that in somecases the adder is considered part of the 2D equalizer, as shown in FIG.2B, whereas in other cases the adder is considered as receiving theoutput lines of the 2D equalizer, as shown in FIGS. 3A and 3B. In anycase, the TDMR system decodes one track using two signals that aregenerated from more than the one track, and so appropriate weights areused with each signal.

However, the TDMR architecture 290 includes different read channels 294,296 in that the FIR filters have been removed. This reduces the lengthof the critical path (from read head to data detector) and reducescontrol loop latency. In addition, by using a primary headconfiguration, such as configuration 180 in FIG. 1E, where one of theheads is largely on track, with the center of H1 182 aligned with thecenter of the track so as to get most of its signal from the track beingread, the TDMR architecture 290 can exploit this primary head geometryconfiguration and only include one additional FIR 292 for driving frontend control loops (ASC, VGA, and timing loops). Thus, hardware costs canbe reduced as compared with the TDMR architecture 200. Moreover, as ispossible in the TDMR architecture 200, the TDMR architecture 290 usesone error signal (in this case generated from FIR 292, which is outsideof the read channel) to drive one DTL 280 to control two interpolators282, 284.

In some cases though, it may be desirable to reduce latency and hardwarecosts without requiring a primary head configuration. FIG. 3A shows athird example 300 of a system architecture for TDMR read circuitry,which can be used with no primary head, such as head geometry 190 fromFIG. 1F. Many of the components of the TDMR architecture 300 are thesame as the TDMR architecture 200, as shown by common reference numbers,and so are not described again here. In the TDMR architecture 300, the2D equalization is performed directly on ADC samples, but the loops aredriven from a 2D equalizer error signal. Note that this reduces by oneagain the number of FIR filters since only two FIR filters are used(FIR1 and FIR2 in the 2D equalizer 250).

Connecting the components of the TDMR architecture 300 as shown in FIG.3A, the output of the BL unit 260 and the decisions convolved with thetarget can be used to generate the error signal after the 2D equalizer250. This error signal can be used to drive the gain loop, the asymmetryloop, and the timing loop for both read channels 294, 296, includingdriving AGC 310, AGC2 312, ASM 314, ASM2 316, and DTL 320. Thus, theTDMR architecture 300 waits for the 2D equalizer 250 output to generatethe error signal from which the front end loops are driven, and there isno need for one of the heads 182, 186 to be largely on track. The tworead heads can be anywhere. Note that the error signal and be generatedas the difference of equalizer output and reconstructed Viterbi output,in this case using the 2D EQ 350 output. The AGC 310 and AGC2 312 canuse error signal and component FIR outputs to drive their respectiveloops. In addition, the ASC2 234 can be driven by ASM2 316, which canhave its own input.

As with TDMR architectures 200 and 290, the TDMR architecture 300 alsoincludes two interpolators (ITERP 322 and ITERP2 324), but this is stillone digital timing loop. Not that in all the architectures there is onlyone digital timing loop because only one track is being read, eventhough the analog signals rise from data recorded on more than onetrack. Thus, the components of the TDRM architecture should lock to thetiming of the one track being read. However, in some implementations,two separate interpolators need not be used.

FIG. 3B shows a fourth example 330 of a system architecture for TDMRread circuitry. Many of the components of the TDMR architecture 330 arethe same as the TDMR architectures 200 and 300, as shown by commonreference numbers, and so are not described again here. However, in theTDMR architecture 330, only a single interpolator 340 is used, and amodified 2D equalizer 350 is employed. This can simplify thearchitecture significantly.

As noted above, the programmable delay lines 222, 242 can be programmedto account for timing differences between the two read signals that areinteger amounts of the clock cycle used by the TDMR device. In addition,the single interpolator 340 can be used for any needed finer adjustmentsthat are less than an individual clock cycle and are common between thetwo read signals. But rather than accounting for timing differences thatare fractional amounts (less than one) of the clock cycle using twoseparate interpolators, which involves added design complexity forsynchronization, any fractional difference (less than one clock cycle)between the two read signals can be resolved by the FIR filters in the2D equalizer 350.

For example, the two FIR filters in the 2D equalizer 350 can each be aten tap FIR filter, which can adjust the delay of the signal beingprocessed anywhere from zero to ten t (t being equal to one clock cycleof the device), even any fractional delay. Thus, by adjusting thecoefficients of FIR1 and FIR2 in the 2D equalizer 350, the fractionaltiming difference between the two read signals can be removed. Forexample, referring to FIGS. 1D and 3B together, if the offset 176between read heads 172 and 174 causes a signal timing difference of 5.6t between the two read signals, 5 t of this timing difference can beremoved by adjusting the values N and N2 input to registers in theprogrammable delay lines 222 and 242, and the remaining signal timingdifference of 0.6 t between the two read signals can be removed byadjusting the coefficients of Fill and FIR2 in the 2D equalizer 350.

This approach can simplify the design significantly since a single clockcan be generated to drive all the circuitry of the DTL 320 andinterpolator 340, rather than having two synchronized clocks output fromthe DTL 320. Note that an interpolator is typically complicatedcircuitry that operates on a fraction of t, e.g., an interpolator cangenerate any resolution down to 1/128 of a clock cycle, and suchresolution numbers also need to be programmed. This is complicated froma circuit design perspective since the two clocks need to besynchronized at some point, such as before the signals are combined,which can be complicated to achieve with high frequency clocks. Byreducing the architecture to one interpolator, the circuit designcomplexity is substantially reduced. Moreover, this single interpolatorapproach can be used in each of the TDMR architectures 200, 290, 300.Thus, the 2D equalizer 250 in each of these TDMR architectures can alsohandle a portion of the alignment of the two read signals.

FIG. 4 is a flowchart showing an example of reading stored data in aTDMR storage system. In some implementations, at 600, a center of afirst read head is aligned with a center of the track being read fromthe TDMR storage medium. For example, the read head 182 that generatesthe first analog read signal in the first read channel can be alignedwith the track, as in the TDMR architecture 290 of FIG. 2B, orpotentially the TDMR architecture 200 of FIG. 2A.

At 610, the first and second analog read signals from respective readheads are processed in separate read channels of a TDMR device, wherethe processing includes separate analog to digital conversions of therespective first and second analog read signals. The first and secondanalog read signals can be from respective first and second portions ofthe TDMR medium, such as described above in connection with FIGS. 1D-1F.Thus, the first portion and the second portion at least partiallyoverlap with a track on the TDMR storage medium.

In addition, the processing can include, in each of the separate readchannels, high pass filtering, asymmetry control, variable gainamplification and continuous time filtering, before the separate analogto digital conversions. The processing can further include delaying afirst digital output signal of a first of the separate analog to digitalconversions by a first programmed amount of time and delaying a seconddigital output signal of a second of the separate analog to digitalconversions by a second programmed amount of time. Moreover, in someimplementations, the processing includes filtering both of the delayeddigital output signals in the separate read channels using respectivefinite impulse response filters, such as described above in connectionwith FIG. 2A, and the processing can include copying taps from the firstfinite impulse response filter to the second finite impulse responsefilter so the first finite impulse response filter and the second finiteimpulse response filter act as duplicates of each other.

In other implementations, no filtering is done within the read channelsin the digital domain before TDMR filtering. For example, in someimplementations, a digital output signal of the read channel for thesignal from the head aligned at 600 to the track is filtered using afinite impulse response filter that is outside of the critical path ofthe read channel, at 620. In other implementations, this filtering at620 is not used, and only the TDMR filtering is employed.

At 630, the digital outputs of the separate analog to digitalconversions are filtered in a TDMR equalizer. In differentimplementations, this filtering can be performed on outputs from FIRfilters in the read channels, or on delayed ADC samples directly. Insome implementations, at 640, a single interpolation of timing ofsampling for each of the separate analog to digital conversions isperformed, and coefficients of filters in the TDMR equalizer areadjusted to account for a timing difference between the first and secondanalog read signals. As described above, this timing difference handledin the TDMR equalizer can be a fractional amount of a single clock cycleof the TCMR device, where the fractional amount is less than the time ofthe single clock cycle.

At 650, one or more error signals are generated to drive the font endloops of the first and second read channels. In some implementations,this can be one or more error signals generated from one or more outputsof the TDMR equalizer to drive asymmetry correction and variable gainamplification for both the first analog read signal and the secondanalog read signal, and to drive the single interpolation at 640. Inother implementations, this can be a single error signal generated fromthe filtered digital output signal generated at 620, where this singleerror signal is used to drive asymmetry correction and variable gainamplification for both the first analog read signal and the secondanalog read signal, and to drive the single interpolation at 640.

A few embodiments have been described in detail above, and variousmodifications are possible. The disclosed subject matter, including thefunctional operations described in this specification, can beimplemented in electronic circuitry, computer hardware, firmware,software, or in combinations of them, such as the structural meansdisclosed in this specification and structural equivalents thereof,including potentially a program operable to cause one or more dataprocessing apparatus to perform the operations described (such as aprogram encoded in a computer-readable medium, which can be a memorydevice, a stage device, a machine-readable storage substrate, or otherphysical, machine-readable medium, or a combination of one or more ofthem).

The term “data processing apparatus” encompasses all apparatus, devices,and machines for processing data, including by way of example aprogrammable processor, a computer, or multiple processors or computers.The apparatus can include, in addition to hardware, code that creates anexecution environment for the computer program in question, e.g., codethat constitutes processor firm ware, a protocol stack, a databasemanagement system, an operating system or a combination of one or moreof them.

A program (also known as a computer program, software, softwareapplication, script, or code) can be written in any form of programminglanguage, including compiled or interpreted languages, or declarative orprocedural languages, and it can be deployed in any form, including as astand alone program or as a module, component, subroutine, or other unitsuitable for use in a computing environment. A program does notnecessarily correspond to a file in a file system. A program can bestored in a portion of a file that holds other programs or data (e.g.,one or more scripts stored in a markup language document), in a singlefile dedicated to the program in question, or in multiple coordinatedfiles (e.g., files that store one or more modules, sub programs, orportions of code). A program can be deployed to be executed on onecomputer or on multiple computers that are located at one site ordistributed across multiple sites and interconnected by a communicationnetwork.

While this specification contains many specifics, these should not beconstrued as limitations on the scope of what may be claimed, but ratheras descriptions of features that may be specific to particularembodiments. Certain features that are described in this specificationin the context of separate embodiments can also be implemented incombination in a single embodiment. Conversely, various features thatare described in the context of a single embodiment can also beimplemented in multiple embodiments separately or in any suitablesubcombination. Moreover, although features may be described above asacting in certain combinations and even initially claimed as such, oneor more features from a claimed combination can in some cases be excisedfrom the combination, and the claimed combination may be directed to asubcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particularorder, this should not be understood as requiring that such operationsbe performed in the particular order shown or in sequential order, orthat all illustrated operations be performed, to achieve desirableresults. Moreover, the separation of various system components in theembodiments described above should not be understood as requiring suchseparation in all embodiment.

Other embodiments fall within the scope of the following claims.

What is claimed is:
 1. A device comprising: a first read channel toprocess a first input signal obtained from a storage medium using afirst read head, wherein the first read channel comprises a first analogto digital converter; a second read channel to process a second inputsignal obtained from the storage medium using a second read head,wherein the second read channel comprises a second analog to digitalconverter; a single digital timing loop for both the first read channeland the second read channel, wherein the single digital timing loop isconfigured to control interpolation of timing of sampling for the firstand second analog to digital converters; and a two dimensional equalizercoupled with output lines of the first read channel and the second readchannel; wherein the first read head and the second read head are offsetfrom each other in each of two dimensions; and wherein the device isconfigured to account for a fractional timing difference between thefirst input signal and the second input signal, the fractional timingdifference being a fractional amount, less than one, of a single clockcycle of the device.
 2. The device of claim 1, comprising: a firstinterpolator for the first analog to digital converter, the firstinterpolator coupled with the single digital timing loop for control ofthe first interpolator by the single digital timing loop; and a secondinterpolator for the second analog to digital converter, the secondinterpolator coupled with the single digital timing loop for control ofthe second interpolator by the single digital timing loop; wherein thefirst and second interpolators are configured to account for thefractional timing difference between the first input signal and thesecond input signal.
 3. The device of claim 2, wherein each of the firstand second interpolators has a resolution of 1/128 of the single clockcycle.
 4. The device of claim 2, wherein the first read channel furthercomprises a first asymmetry correction block, a first variable gainamplifier, and a first programmable delay line; the second read channelfurther comprises a second asymmetry correction block, a second variablegain amplifier, and a second programmable delay line; and the devicefurther comprises: an adaptive finite impulse response unit lyingoutside of the first and second read channels; and a baseline unitconfigured to generate an error signal to control the adaptive finiteimpulse response unit, the variable gain amplifiers, and the singledigital timing loop.
 5. The device of claim 4, wherein: the first readchannel further comprises a first finite impulse response filter coupledwith the adaptive finite impulse response unit; the second read channelfurther comprises a second finite impulse response filter; and thedevice is configured to copy finite impulse response filter taps for thefirst finite impulse response filter from the first finite impulseresponse filter to the second finite impulse response filter.
 6. Thedevice of claim 4, further comprising a finite impulse response filterlying outside of the first and second read channels, the finite impulseresponse filter having an input line coupled with an output line of thefirst programmable delay line, and the finite impulse response filterbeing coupled between the adaptive finite impulse response unit and thebaseline unit to generate the error signal.
 7. The device of claim 2,wherein: the first read channel further comprises a first asymmetrycorrection block, a first variable gain amplifier, and a firstprogrammable delay line; the second read channel further comprises asecond asymmetry correction block, a second variable gain amplifier, anda second programmable delay line; and the device is configured togenerate an error signal from an output of the two dimensional equalizerto drive the variable gain amplifiers and the single digital timingloop.
 8. The device of claim 1, wherein the device is configured toadjust coefficients on taps of respective finite impulse responsefilters in the two dimensional equalizer to account for the fractionaltiming difference between the first input signal and the second inputsignal.
 9. A system comprising: a storage apparatus comprising amagnetic media disk, which is mounted on a spindle and motor assembly,and a head assembly comprising at least a first read head and a secondread head, wherein the first read head and the second read head areoffset from each other in each of two dimensions; and a storagecontroller coupled with the storage apparatus, the storage controllercomprising a first read channel to process a first input signal obtainedfrom the magnetic media disk of the storage apparatus using the firstread head, and a second read channel to process a second input signalobtained from the magnetic media disk of the storage apparatus using thesecond read head; wherein the first read channel comprises a firstanalog to digital converter, the second read channel comprises a secondanalog to digital converter; and wherein the storage controllercomprises a single digital timing loop for both the first read channeland the second read channel, the single digital timing loop beingconfigured to control interpolation of timing of sampling for the firstand second analog to digital converters, the storage controllercomprises a two dimensional equalizer coupled with output lines of thefirst read channel and the second read channel, and the storagecontroller is configured to account for a fractional timing differencebetween the first input signal and the second input signal, thefractional timing difference being a fractional amount, less than one,of a single clock cycle of the device.
 10. The system of claim 9,wherein the storage controller comprises: a first interpolator for thefirst analog to digital converter, the first interpolator coupled withthe single digital timing loop for control of the first interpolator bythe single digital timing loop; and a second interpolator for the secondanalog to digital converter, the second interpolator coupled with thesingle digital timing loop for control of the second interpolator by thesingle digital timing loop; wherein the first and second interpolatorsare configured to account for the fractional timing difference betweenthe first input signal and the second input signal.
 11. The system ofclaim 10, wherein each of the first and second interpolators has aresolution of 1/128 of the single clock cycle.
 12. The system of claim10, wherein the first read channel further comprises a first asymmetrycorrection block, a first variable gain amplifier, and a firstprogrammable delay line; the second read channel further comprises asecond asymmetry correction block, a second variable gain amplifier, anda second programmable delay line; and the storage controller furthercomprises: an adaptive finite impulse response unit lying outside of thefirst and second read channels; and a baseline unit configured togenerate an error signal to control the adaptive finite impulse responseunit, the variable gain amplifiers, and the single digital timing loop.13. The system of claim 12, wherein: the first read channel furthercomprises a first finite impulse response filter coupled with theadaptive finite impulse response unit; the second read channel furthercomprises a second finite impulse response filter; and the storagecontroller is configured to copy finite impulse response filter taps forthe first finite impulse response filter from the first finite impulseresponse filter to the second finite impulse response filter.
 14. Thesystem of claim 12, wherein the storage controller further comprises afinite impulse response filter lying outside of the first and secondread channels, the finite impulse response filter having an input linecoupled with an output line of the first programmable delay line, andthe finite impulse response filter being coupled between the adaptivefinite impulse response unit and the baseline unit to generate the errorsignal.
 15. The system of claim 10, wherein: the first read channelfurther comprises a first asymmetry correction block, a first variablegain amplifier, and a first programmable delay line; the second readchannel further comprises a second asymmetry correction block, a secondvariable gain amplifier, and a second programmable delay line; and thestorage controller is configured to generate an error signal from anoutput of the two dimensional equalizer to drive the variable gainamplifiers and the single digital timing loop.
 16. The system of claim9, wherein the storage controller is configured to adjust coefficientson taps of respective finite impulse response filters in the twodimensional equalizer to account for the fractional timing differencebetween the first input signal and the second input signal.
 17. A methodcomprising: processing, in a first read channel, a first input signalobtained from a storage medium using a first read head, wherein thefirst read channel comprises a first analog to digital converter;processing, in a second read channel, a second input signal obtainedfrom the storage medium using a second read head, wherein the secondread channel comprises a second analog to digital converter, and thefirst read head and the second read head are offset from each other ineach of two dimensions; controlling interpolation of timing of samplingfor the first and second analog to digital converters using a singledigital timing loop for both the first read channel and the second readchannel; performing two dimensional equalization on outputs of the firstread channel and the second read channel; and accounting for afractional timing difference between the first input signal and thesecond input signal, the fractional timing difference being a fractionalamount, less than one, of a single clock cycle.
 18. The method of claim17, wherein the accounting comprises using two separate interpolatorscoupled with the single digital timing loop.
 19. The method of claim 17,wherein the first read channel further comprises a first asymmetrycorrection block, a first variable gain amplifier, and a firstprogrammable delay line; the second read channel further comprises asecond asymmetry correction block, a second variable gain amplifier, anda second programmable delay line; and the method comprises: generatingan error signal from an output of the two dimensional equalization todrive the variable gain amplifiers and the single digital timing loop.20. The method of claim 17, wherein the accounting comprises adjustingcoefficients on taps of respective finite impulse response filtersperforming the two dimensional equalization.